Whereas the processing of binary data in digital data terminal equipment usually occurs in parallel data structure, the serial data structure is preferred for the transmission of binary data between data terminal equipment such as can be established, for example, by a connection between data terminal equipment of a LAN (local area network).
A module for serial-to-parallel-to-serial conversion of digital data words is known in the prior art (for example, European reference EP-A1 0 251 151) that is programmable such that data words that are shorter than the length of the built-in register for serial-to-parallel conversion can also be converted. For converting data words that are longer than the length of the register of serial-to-parallel conversion built into the module, an appropriate number of such modules are cascaded. Regardless of the data word length to be converted, however, the entire length of the respective data word is always read into or, respectively, read out from the register for serial-to-parallel conversion in parallel.
With increasing word length, there is a disadvantageous effect that the high number of simultaneously occurring switchings during a clock step leads to high loading peaks of the supplying operating voltage source and, thus, to high clock loads.
For bi-directional conversion of data words having a parallel structure into data words having a serial structure, the reference SIEMENS-Datenbuch Mikroprozessorbausteine, Edition 1976/77 discloses a module SAB 8251 that has function blocks that are connected by an internal data bus and control lines. The function blocks include a serial-to-parallel converter, a parallel-to-serial converter, a register for buffering data present in parallel structure and various controls. In this module, data words are always converted in their entire data word length, a length of 8 bits in the given case. When this concept is applied to the conversion of long data words as can be established, for example, by data words having a length of 512 bits, then high clock loads also occur for this module.
When the data rate is high in addition to the length of the data words to be processed, than a correspondingly high dissipated power also occurs for the known modules. Furthermore, given serial-to-parallel conversion and high data rates, it is difficult to continuously transfer serial data entering a register into the long shift register or, respectively, it is difficult to load the entire shift register in the parallel-to-serial conversion since less than 1 bit time is available for this event.